| http://www.w3.org/ns/prov#value | - ith an (n) bit selection, wherein n is an integer greater than or equal to one, as delay clock signals having a maximum of m=2n steps, wherein m is an integer greater than or equal to one; second delay means for fine adjustment, said first and second delay means connected in cascade, said second delay means selectively outputting the input clock signal in accordance with a (p) bit selection signal
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