| http://www.w3.org/ns/prov#value | - a nonvolatile memory device coupled to the processor, the nonvolatile memory device including circuitry to allow dynamic partitioning of memory within the nonvolatile memory device and including at least two interfaces to access partitions within the nonvolatile memory device, wherein the at least two interfaces include read buffers of different sizes and write buffers of different sizes.
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