| http://www.w3.org/ns/prov#value | - FIG. 5 is a second timing chart for describing the operation ofthe synchronization circuit 100 of the first embodiment of the invention.In the synchronization circuit 100, when the flip-flop circuit 110 enters a metastable state at the rising edge T1 of the system clock SCK, the output signal SYNC1 of the flip-flop circuit 110 is converged to the H-level after an unstable stateof a metastable peri
|
