| http://www.w3.org/ns/prov#value | - FIG. 5 is a plan view showing the semiconductor wafer condition and FIG. 6 is a plan view showing the semiconductor chip condition. [0067] First, in regard to the semiconductor chip 2 of flash memory, the wafer processes such as oxidation/diffusion/implantation of impurities, formation of wiring patterns, formation of insulation layers and formation of wiring layers are repeatedly conducted to for
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