| http://www.w3.org/ns/prov#value | - FIG. 9A is a plan view of an individual chip package having a capacitor suitable for use in the three dimensional stack package device according to the present invention, and FIG. 9B is a cross sectional view taken along the line 9B--9B in FIG. 9A. The capacitor 20 is connected between power supply terminal Vcc and the ground terminal GND so that power noise of the chip can be effectively improved
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