| http://www.w3.org/ns/prov#value | - FIG. 15A is a timing chart for the vertical sync signal (ITOP) 29 and horizontal sync signal (HSYNC) 28 which are input to the address generating unit when the image formation of four times is executed, the more significant address 204 in the full page image memory 304 which is generated from the address generating unit, palette data 326 which is read out of the full page image memory on the basis
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