| http://www.w3.org/ns/prov#value | - FIG. 7B is a flowchart of an exemplary processing routine in a proposed stream scalar ALU combined with an SFU, while FIG. 7C is a continuation of FIG. 7B. According to the nonlimiting examples of FIGS. 7B and 7C, SIMD stream processor with scalar ALUs can process 4 sets of graphics vector data simultaneously and it takes 10 instruction cycles (9+1) versus 16 cycles in traditional vector architect
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