| http://www.w3.org/ns/prov#value | - Preferably, the Si layer 24 is thicker than the Si layer 18 of the NFET region, with a range for the Si layer 24 being between 200 .ANG. and 600 .ANG., with a delta of at least 100 .ANG. between NFET Si layer 18 and PFET Si layer 24.FIGS. 1d through 1i show the fabrication process of the gate structures, including the source and drain (S/D) regions for the NFET and PFET channel, respectively.
|
