| http://www.w3.org/ns/prov#value | - BRIEF DESCRIPTION OF THE DRAWINGS [0007]FIG. 1 illustrates, as an example, a flow diagram of a method for performing circuit area analysis including a method for eliminating false failures saved by redundant paths during the circuit area analysis, utilizing aspects of the present invention. [0008] FIGS. 2???3 illustrate, as an example, a method for generating predefined sets of vertices for nets o
|
