| http://www.w3.org/ns/prov#value | - FIG. 1B is a circuit diagram schematically showing a configuration example of the bus communication transceiver LTr in the first embodiment, and especially, the more detailed configuration of the delay time measurement circuit section DTM and the output waveform adjustment circuit section OWR. Of the bus communication transceiver LTr shown in FIG. 1B, the components of the delay time measurement c
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