| http://www.w3.org/ns/prov#value | - In the embodiments shown in FIGS. 15 and 18B, the delay operator Z-1 is commonly used in both FIGS. 14A and 14B. Alternatively, a memory and a transmission circuit, for example may be inserted between the circuits corresponding to FIGS. 14A and 14B. The full scale XFS of the A/D converter, that is, the maximum allowable input level, the number N of the converting bits, the converting code may be p
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