| http://www.w3.org/ns/prov#value | - FIG. 3 is a flow chart showing a processing procedure of the CPU 210 shown in FIG. 2; FIG. 4 is a timing chart showing an operation of each portion of FIG. 2 when data are normally received from the host, that is, when the host transmits subsequent data after the host transmits one byte of data and then the third busy control circuit 230 generates the busy signal BUSY-- OUT; and FIG. 5 is a timing
|
