| http://www.w3.org/ns/prov#value | - In an arrangement such as shown in FIG. 1 where row decoder 14 is located centrally, with array blocks 12 on either side thereof, it is preferred that the most significant column address bit (address terminal Aj in this embodiment) also be decoded by master row decoder 14, so that the row line may be energized only on the one side of master row decoder 14 corresponding to the most significant colu
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