| http://www.w3.org/ns/prov#value | - In a case where the instruction is a memory access instruction, moreover, access to not only the RISC load/store unit 127 but also the data cache 129 occurs via an address bus 126, so that data is stored in the registers of the integer arithmetic unit 119 and the floating-point arithmetic unit 118 via a data bus 128 and a data bus 121 for RISC. When applicable data is absent (cache miss) in the da
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