| http://www.w3.org/ns/prov#value | - ncluding the first source/drain region, the access transistor including at least a first gate on a first side of the pillar; a plurality of bit lines implanted into the substrate, each of the plurality of bit lines in conductive contact with the first source/drain region of the access transistor of at least a plurality of memory cells in a common column of the array; and a plurality of word lines
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