| http://www.w3.org/ns/prov#value | - FIG. 5 is a timing chart showing the relationship between the input signal applied to the receiver circuit 5 through the data receiving pin RD and on/off control of the analog switch SW. FIG. 5 (a) shows the input signal, FIG. 5 (b) shows the output signal of the receiver circuit 5, and FIGS. 5 (c) and 5 (d) show on/off timing of the analog switch SW. FIG. 5 (c) shows the operation timing of the a
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