| http://www.w3.org/ns/prov#value | - 20090319971METHOD OF VERIFYING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An exemplary aspect of an embodiment of the present Invention is a method of verifying a layout for a semiconductor integrated circuit device including: segmenting a layout of a semiconductor integrated circuit device into a plurality of local regions; calculating a ratio for each local region, the ratio being the a
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