| http://www.w3.org/ns/prov#value | - In some embodiments, such as the embodiment in which the bus 113 is a PCI-E bus, the peer to peer communication protocol used by the peer GPUs 122(0) and 122(1) does not allow a peer to initiate read operations of the graphics memory 124(0) and 124(1) of the peer GPU. Thus, a first GPU 122(0) cannot initiate a read of the graphics memory 124(1) local to the second GPU 122(1) to ensure that the flu
|
