| http://www.w3.org/ns/prov#value | - In FIGS. 9A and 9B, the Din input of memory array MA is connected to the output line of multiplexer M18 where the input lines of multiplexer M18 are connected the same as in the DPD. Gate L19, however, is an AND gate, rather than a NOT gate, and inputs signals R2 and S/D* such that if signal S/D* is high, the low-input line of multiplexer M18 is always selected and if signal S/D* is low, gate L19
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