| http://www.w3.org/ns/prov#value | - ignal???, for receiving a write signal from the CPU 130 as an ENABLE signal and for receiving a Vcc_PWR.GOOD signal and outputting either the ???perform reset??? or ???ignore reset signal??? as an output control signal, wherein write signal is a signal which is generated when CPU 130 writes data to a memory, thus when the data is the above mentioned control signal the inhibit register 220 is addre
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