| http://www.w3.org/ns/prov#value | - FIG. 4A is a circuit diagram of the Common Front End (CFE) card of the data link processor and FIG. 4A is shown on two sheets which are designated as FIGS. 4A-1 and 4A-2; FIG. 4B is a circuit of the Common Front End clear circuitry; FIG. 4C shows the clock control circuitry for the CFE; FIG. 4D shows the connection logic circuitry of the Common Front End; FIG. 4E is a timing diagram showing how da
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