| http://www.w3.org/ns/prov#value | - BRIEF DESCRIPTION OF THE DRAWINGS [0019]FIG. 1 is a circuit diagram of a static random access memory (SRAM) cell consisting of the combination of two NDR elements which form a bistable latch and one n-channel enhancement-mode IGFET access element, wherein at least one of the NDR elements is an NDR FET, and the other NDR element is an NDR FET configured to operate like an NDR diode; [0020]FIG. 2 is
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