| http://www.w3.org/ns/prov#value | - FIG. 2 is a more detailed illustration of a possible implementation of the sorting and compare circuits of FIG. 1 showing, in the former instance, a number of alternating inverting amplifiers and clocked latch circuits for providing DATA0 and DATA1 outputs in response to a DDR data input and, in the latter instance, the logic for providing compressed SDR data output in response to the DATA0 and DA
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