| http://www.w3.org/ns/prov#value | - FIG. 7 is a plan view showing only an active region and source and drain regions of a CMOS circuit which is a complementary combination of an n-channel type pinning FET and a p-channel type pinning FET. 701 designates the source region of the n-channel type pinning FET. 702 designates the drain region of the same. 704 designates the source region of the p-channel type pinning FET. 705 designates t
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