| http://www.w3.org/ns/prov#value | - FIG. 1B is a circuit diagram of a prior art embodiment of the load circuitry of FIG. 1a; FIG. 1 is a circuit diagram of another prior art embodiment of the load circuitry of FIG. 1a; FIG. 2 is a waveform diagram illustrating the change in the differential loop state information as the delay locked loop circuit of FIG. 1a transitions from normal operating mode to low power mode and back to normal o
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