| http://www.w3.org/ns/prov#value | - FIG. 3 is a flow chart illustrating the processes embodied in the present invention, as used in the system of FIG. 1, including FIG. 3A illustrating the process for analyzing a digital circuit for indirect implication, FIG. 3B illustrating the process for determining when a partition of a logic circuit design is complete for carrying out logic design verification, and FIG. 3C illustrating the proc
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