| http://www.w3.org/ns/prov#value | - FIG. 4A is a circuit diagram of another embodiment of the voltage level converter VLC in accordance with the present invention modified in view of the above requirement, and FIG. 4B illustrates pulse waveforms of an input pulse and signals at four nodes in the voltage level converter of FIG. 4A. FIG. 4A is a circuit diagram similar to that of FIG. 3, except that a CMOS inverter is added whose inpu
|
