| http://www.w3.org/ns/prov#value | - input and produces an output, (b) divider means for receiving said output from said extraction means as an input having a first frequency and producing an output having a second frequency that is 1/n said first frequency, where n is an integer greater than one, (c) high Q means for reducing timing jitter, said high Q means receiving said output from said divider circuit and producing a final clock
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