| http://www.w3.org/ns/prov#value | - each of FIGS. 3, 4, and 5 is a schematic diagram of a different form the electrically erasable programmable non-volatile memory portion of the FIG. 1 circuit may take in accordance with different embodiments of the invention, each using at least one pair of complementary-conductivity programmable-threshold-voltage FETs;
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