| http://www.w3.org/ns/prov#value | - Except for the manner in which addresses are latched into the address buffers, a synchronous operation (either a synchronous burst read, a synchronous burst write operation, a synchronous wrap read operation, or a synchronous wrap write operation) of the synchronous memory device 30 of FIG. 2 is accomplished in a manner which is similar to the operation described in the aforementioned U.S. Pat. No
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