About: http://webisa.webdatacommons.org/288630214

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	FIG. 5 is a timing chart of current signals that are output from the main buffer circuit 10 and the pre-emphasis buffer circuit 20 respectively;
http://www.w3.org/ns/prov#wasQuotedFrom	google.com