| http://www.w3.org/ns/prov#value | - As shown in FIG. 16, the selection control signal generating circuit 30 is a circuit for generating the division timing signals (DIV1 to DIV4) that are used to divide the period defined by the control signal DIVSEL into a plurality of periods, and is composed of two flip-flops FF1 and FF2 and a counter consisting of a plurality of (four) logic gate circuits G1 to G4 combined together.
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