| http://www.w3.org/ns/prov#value | - A reduced-capacitance current steering circuit configured to reduce data-switching-induced capacitive effects, comprising:a current steering circuit including a current source biased to feed a substantially constant current into a summing node, where the current is steered either to an output leg or to a ground leg; a data-switched MOS transistor coupled into one of the circuit legs for controllin
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