| http://www.w3.org/ns/prov#value | - Lightly doped source/drain areas are formed adjacent to the gate electrodes, usually by ion implantation of an N-type dopant such as arsenic (As) or phosphorus (P), and then sidewall spacers are formed on the gate electrode sidewalls, by depositing a conformal insulating (SiO2) layer and anisotropically etching back the layer to the substrate surface.
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