| http://www.w3.org/ns/prov#value | - he memory; [0017]FIG. 3 is a block diagram of a computer system including a central processing unit having a stack cache implemented in accordance with one embodiment of the present invention; [0018]FIG. 4 is a block diagram of one embodiment of the stack cache of FIG. 3; [0019]FIG. 5 is a flow chart illustrating one embodiment of a register spill operation for the stack cache of FIG. 4; [0020]FIG
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