| http://www.w3.org/ns/prov#value | - The memory module of claim 23, wherein if a first of the at least two second memories has a write latency of n, where n is an integer greater than zero, a read latency of m, where m is an integer greater than one, a burst length of k, where k is an integer greater than one, and a clock period of j, where j is an integer greater than one, corresponding to the burst length, a second of the at least
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