| http://www.w3.org/ns/prov#value | - The translator of claim 1, wherein said PCI memory cycle is a PCI memory write cycle, wherein said PCI memory write cycle further includes data, wherein said IEEE 1394 initiator is operable to receive said data and provide said data to said packet dispatcher logic, wherein said request packet is a write request packet, wherein said packet dispatcher logic is operable to include said data in a data
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