| http://www.w3.org/ns/prov#value | - This memory controller comprises: [0056] n ECC/ChIPKILL circuits connected to respective n memory slots, for ECC code generation, error check, data reconfiguration, and ChipKill operation, where n is an integer greater than one; [0057] a parity-generation/check/reconfiguration circuit connected to the n ECC/CHIPKILL circuits, the parity-generation/check/reconfiguration circuit defining one of n me
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