| http://www.w3.org/ns/prov#value | - The gate driver includes a first shift register for sequentially outputting n scan pulses (where n is a natural number larger than 2), and a second shift register for selecting p ones (where p is a natural number smaller than or equal to n) of the n scan pulses from the first shift register in response to an external output control signal and supplying the selected p scan pulses respectively to p
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