| http://www.w3.org/ns/prov#value | - The data controllers 46A, 46B, for instance, are configured from a switch such as a crossbar switch or a bus for performing data transmission via high-speed switching, are connected to the channel controllers 42A, 42B, disk controllers 43A, 43B, cache memories 44A, 44B and shared memories 45A, 45B, and transfer the data write request, data read request, data to be written and data to be read among
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