| http://www.w3.org/ns/prov#value | - The controller of claim 20, wherein said receive FIFO is defined by START and END pointers, and including READ and WRITE pointers, a SHADOW WRITE pointer pointing to the beginning of the latest frame being received in the receive FIFO, and a receive threshold value, wherein said receive data is transferred to said system memory means when said write pointer exceed said threshold value and when sai
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