| http://www.w3.org/ns/prov#value | - The system of claim 1, wherein the number of the plurality of memory modules is equal to N, where N is a positive integer, and wherein the memory test device accesses the memory storage units in the portion of the plurality of memory storage units in the repeated sequence based on a plurality of programmable stride values, such that the memory storage units in the portion of the plurality of memor
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