| http://www.w3.org/ns/prov#value | - The method of claim 53 wherein the computer system performance to be optimized is for prefetching of data into a prefetch cache, where the increment amount Ci(t0, t1, t2, . . . , tj) is given by min(T, tj???tj???i???1), T is a memory latency for the computer system, the side information tl, 0???l???j, is a time not including stall times at which an outcome xl occurs in central processing unit cycl
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