| http://www.w3.org/ns/prov#value | - The system includes a circuit 57 for switching and issuing control data and other digital data, a switching circuit 52 for selectively issuing SWS data to a D/A converter 9 and other digital data to an interface circuit 53, a block counter 63 for counting pulses in each period of one block when data items are fed to a large capacity buffer memory 5, the block counter 63 being reset by a pulse from
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