| http://www.w3.org/ns/prov#value | - The bus bridge as set forth in claim 21, wherein each of the bridge portals other than the cycle monster portal includes:a modulo N ??s counter which receives the cycle counter output of the respective cycle clock subsystem and which produces a timing signal every N ??s in response thereto, where N is a value specified by a prescribed bus protocol; a state machine which produces a channel request
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