| http://www.w3.org/ns/prov#value | - A highly interleaved memory system comprising: a plurality of central processing units selectively connected by a switching network to 2n +1, 2n, or 2n -1 memory modules where n is a positive integer, said central processing units including means for generating two address components for a logical address of one of said memory modules, one address component selecting a memory module and another ad
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