| http://www.w3.org/ns/prov#value | - When such a configuration as described above is adopted, the area occupied by the alignment mark arrangement regions on the wafer becomes smaller, and the number of chips per wafer is increased accordingly.A method of patterning a wafer using a reticle substrate illustrated in FIG. 3 is similar to the method of patterning a wafer using the reticle substrate illustrated in FIG. 1, but differs to a
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