| http://www.w3.org/ns/prov#value | - The semiconductor memory 10 of the preferred embodiment of the present invention is a semiconductor memory having a configuration of a plurality of bits for performing a writing and a reading of data in a unit of a plurality of bits, wherein it is comprised of a memory cell array 11 having a plurality of memory cells of which addresses are determined in a unit of a plurality of bits; an address in
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