| http://www.w3.org/ns/prov#value | - This scheme enhances the robustness of the semiconductor memory device with respect to electrical noise and other disturbances that may occur during operation. [0086] The first embodiment enables defective bits to be detected and isolated to a particular memory cell array and a particular sense amplifier array in a single high-speed test, in which eight bits are tested at once instead of just four
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