| http://www.w3.org/ns/prov#value | - When the memory access request to address 4 is issued to the memory bank 41 (i.e. read latch 97), the busy counter 751 is set to an initial value other then 0 (preferable the worst case number of cycles nC, four in the example to perform a memory read for bank 41 wherein n is a positive integer, four in the example), thereby putting the memory read operation to address 8 and the memory read operat
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